The present invention relates to a semiconductor memory device; and, more particularly, to a memory device performing a write leveling operation introduced from a DDR3 (Double Data Rate 3) memory device.
It is known that the write leveling refers to an operation that calibrates a skew between DQS (data strobe signal) and a clock so as to improve a tDQS margin, a timing difference between the DQS and the clock, during a write operation of a memory device.
Basically, the write leveling operation is done by providing the logic state of a clock at a rising edge of DQS as data DQ after an entry into a write leveling mode by EMRS (Extended Mode Register Set) setting. In other words, if the state of a clock is a logic high level at a rising edge of DQS, a high level data is outputted as data DQ, and if the state thereof is a logic low level, a low level data is provided as data DQ.
FIG. 1 is a block diagram showing a data output unit for explaining a write leveling operation in a conventional DDR3 memory device using an 8-bit prefetch.
A normal operation will be first explained, followed by the write leveling operation. That is, a data is carried on global input/output lines GIO0 to GIO7 by a read command in a memory device.
At a multiplexing unit 10, in response to a data selection signal gaxydb<0:3>, a corresponding data is selected and the selected data GIO_MUX is outputted to a pipe latch unit 20.
The pipe latch unit 20 inputs the data GIO_MUX to the pipe latches 22 to 25 by pipe latch input signals PIN<0:3> being sequentially enabled, and latches them to output data FD0 and RD0 to an output driver 30 by pipe latch output signals POUT<0:3>. A control signal sosez used herein denotes a signal for deciding the output sequence of data latched by pipe latches 22 to 25 included in the pipe latch unit 20. For reference, RD0 in the drawing means data for rising edge and FD0 means data for falling edge.
The operation in the write leveling mode will now be described in detail. First, if the write leveling mode is selected by EMRS setting, a pipe-out circuit 21 included in the pipe latch unit 20 is open by an inverted signal dqslevb of a write leveling signal dqslev being activated and write level data level_data is outputted to the output driver 30 through the pipe-out circuit 21. The write level data level_data herein is the one with the state of a clock at a rising edge of DQS.
Further, in the write leveling mode, the pipe latch input signals PIN<0:3> and the pipe latch output signals POUT<0:3> are all disabled, thereby making all of the pipe latches 22 to 25 excluding the pipe-out circuit 21 closed.
As described above, the conventional memory device is made in a manner that the pipe latch unit 20 is in charge of the output of the write leveling data level_data in the write leveling mode.
FIG. 2 offers a detailed circuit diagram of the pipe-out circuit 21 depicted in FIG. 1.
The pipe-out circuit 21 has the same structure as the output part of the pipe latches 22 to 25. In operation, if the current operation mode becomes the write leveling mode, an inverted signal dqslevb of a write leveling signal is inputted with a logic low level. In response to this, transistors P21 and N22 are turned on, which enables inverters P22 and N21 to output the write leveling data level_data to a node RD0.
In a normal mode, since the inverted signal dqslevb of the write leveling signal is a logic high level, the transistors P21 and N22 are turned off, which enables the inverters P22 and N21 not to output the write leveling data level_data.
FIG. 3 describes a detailed circuit diagram of the multiplexing unit 10 shown in FIG. 1.
In particular, FIG. 3 shows one multiplexer 0 out of the multiplexers 0 to 7 included in the multiplexing unit 10. The conventional multiplexer 0 is configured to include pass gates PG31, PG32, PG33 and PG34 which are turned on depending on the data selection signals gaxydb<0:3> and deliver data on global input/output lines GIO0_0 to GIO0_3 to an output end GIO_MUX0 of the multiplexer 0, but is not concerned in the operation in the write leveling mode.
As set forth above, the conventional memory device is implemented in such a way that the pipe latch unit 20 participates in the write leveling operation. For this, the pipe latch unit 20 is provided with the pipe-out circuit 21 having a relatively large size, thereby causing damage to layout.
In addition, since the pipe latch unit 20 is provided with the pipe-out circuit 21 to participate in the write leveling operation, it increases loading of lines RD0 and FD0 that are output ends of the pipe latch unit 20. As a result, this results in a loss in a tAA value (which is a performance factor representing the speed of data to be outputted from a read command).